1. Field of the Invention
This invention relates generally to apparatus associated with an integrated circuit memory array and, more particularly, to the voltage generators which are used to provide the bias voltage for the substrate in memory arrays.
2. Description of the Related Art
The complementary metal oxide semiconductor (CMOS) devices are constrained by the requirement for high speed operation and by the requirement for low power consumption. These requirements can be achieved, inter alia, by employing new device architecture, reducing the supply voltage, reducing the device size, and utilizing on-chip power management circuit(s). One of the most crucial factors in the further development of memory and logic circuit devices is the availability of transistors that can deliver a high drive current while maintaining low threshold voltage, Vth, and low sub-threshold leakage current. (In addition, the transistors must maintain the drain terminal to source terminal breakdown voltage, minimize "hot" electron carrier injection, exhibit low drain terminal and source terminal capacitance, and exhibit low junction leakage current, etc.) Because the transistor performance parameters are interrelated, the transistors which are finally implemented in a semiconductor device are a compromise of the desired parameters. Certain transistor applications, however, require that the drive current, the threshold voltage, Vth, and the leakage current parameters meet stringent characteristics. In particular, the dynamic random access memory (DRAM) n-channel passgate transistor in the semiconductor memory array must have a low threshold voltage and good drive current for high-speed-charge transfer between the memory cell and the bitline. In addition, the passgate transistor must maintain an extremely low leakage current (to retain the logic state determined by the charge on the capacitor). In order to achieve a high performance passgate transistor, two circuit techniques have been developed to improve the transistor performance:
1) A booted wordline voltage level, VPP, is generated by apparatus on the device substrate to increase the drive strength as well as the speed of the n-channel passgate transistor. A relatively high gate-to-source voltage, Vgs, from the VPP voltage level increases the channel conductance and the fast gate-to-source voltage rise time compensates for the relatively high threshold voltage, Vth, of the passgate transistor. A threshold voltage drop is also eliminated with the VPP voltage level to write a full logic "1" into the storage cell. PA1 2) To reduce the transistor leakage current in the sub-threshold regime and the source-drain capacitance, a negative substrate back bias voltage generator, VBB, is implemented on the DRAM memory array substrate. The VBB voltage generator or pump takes the p-tank substrate region to a fixed negative level (the level being determined by the pump frequency, amplitude, and the Vth of the transistor pumping circuit) to increase the body effect and thus increase the effective Vth of the passgate device. This negative level can also cause the increase in the p-n junction leakage current of the passgate. A VBB generator must provide for both high current drive of the passgate transistor and low leakage current during the standby mode of the DRAM memory unit.
Referring to FIG. 1, a block diagram of the a VBB voltage generator according to the related art is shown. The ENABLE/CONTROL signals are applied to the high and low frequency oscillators unit 11. The oscillators unit 11 applies a periodic signal (with a frequency determined by the control signals) to the VBB pump unit 12. VBB pump unit 12 has an output terminal coupled to the substrate well and applies a bias voltage thereto. The VBB pump unit 12 typically operates by storing a charge on a pump capacitor, one plate of the capacitor being at a first voltage level; changing the voltage level on the capacitor plate to a second voltage level; removing the charge from the capacitor; returning the capacitor plate voltage to the first voltage level; and repeating the procedure. In this manner, the VBB pump unit can provide a voltage level on a semiconductor chip which is outside of the range of the applied voltages, i.e., in the present invention, VBB is less than the lower supply voltage VSS. The voltage levels are typically changed in response to an oscillator signal. Because the VBB is a function of the amount of charge transferred, a limited control of the VBB voltage can be provided by changing the frequency of the oscillator signal, the oscillator signal frequency being a function of ENABLE/CONTROL signals. In FIG. 1, the VPERI is approximately equal to VDD (&gt;VSS). The VBB pump unit 12 provides a substrate bias voltage VBB which is less than VSS.
The VBB pump unit of the related art has had limited capability to respond to the operating modes of the circuit. A need has therefore been felt for a VBB generator which can compensate for leakage current during fast passgate transistor operation in the normal operational mode, for the standby operational mode, or for the self-refresh operational mode.